Intel® Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 9/24/2018
Document Table of Contents

3.5.15. Read Comments as HDL

The read_comments_as_HDL synthesis directive indicates that the Intel® Quartus® Prime software should compile a portion of HDL code that you commented out. This directive allows you to comment out portions of HDL source code that are not relevant for simulation, while instructing the Intel® Quartus® Prime software to read and synthesize that same source code. Setting the read_comments_as_HDL directive to on indicates the beginning of commented code that the synthesis tool should read; setting the read_comments_as_HDL directive to off indicates the end of the code.

Note: You can use this directive with translate_off and translate_on to create one HDL source file that includes an IP core instantiation for synthesis and a behavioral description for simulation.

Formal verification tools do not support the read_comments_as_HDL directive because the tools do not recognize the directive.

In these examples, the Compiler synthesizes the commented code enclosed by read_comments_as_HDL because the directive is visible to the Intel® Quartus® Prime Compiler. VHDL 2008 allows block comments, which comments are also supported for synthesis directives.

Note: Because synthesis directives are case sensitive in Verilog HDL, you must match the case of the directive, as shown in the following examples.
Table 54.  Read Comments as HDL
HDL Code
Verilog HDL
// synthesis read_comments_as_HDL on
// my_rom lpm_rom 	(.address (address),
// 	                 .data    (data));
// synthesis read_comments_as_HDL off
-- synthesis read_comments_as_HDL on
-- my_rom : entity lpm_rom
--   port map (
--    address => address,
--    data    => data,      );
-- synthesis read_comments_as_HDL off
VHDL 2008
/* synthesis read_comments_as_HDL on */
/* my_rom : entity lpm_rom
    port map (
    address => address,
    data => data, ); */
    synthesis read_comments_as_HDL off */