Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Public
Document Table of Contents

3.5.10. Multiplier Style—for Inferred Multipliers

The multstyle attribute specifies the implementation style for multiplication operations (*) in your HDL source code. You can use this attribute to specify whether you prefer the Compiler to implement a multiplication operation in general logic or dedicated hardware, if available in the target device.

The multstyle attribute takes a string value of "logic" or "dsp", indicating a preferred implementation in logic or in dedicated hardware, respectively. In Verilog HDL, apply the attribute to a module declaration, a variable declaration, or a specific binary expression that contains the * operator. In VHDL, apply the synthesis attribute to a signal, variable, entity, or architecture.

Note: Specifying a multstyle of "dsp" does not guarantee that the Quartus® Prime software can implement a multiplication in dedicated DSP hardware. The final implementation depends on several conditions, including the availability of dedicated hardware in the target device, the size of the operands, and whether or not one or both operands are constant.

In addition to multstyle, the Quartus® Prime software supports the syn_multstyle attribute name for compatibility with other synthesis tools.

When applied to a Verilog HDL module declaration, the attribute specifies the default implementation style for all instances of the * operator in the module. For example, in the following code examples, the multstyle attribute directs the Quartus® Prime software to implement all multiplications inside module my_module in the dedicated multiplication hardware.

Table 44.   Applying a multstyle Attribute to a Module Declaration
HDL Code
Verilog-1995
module my_module (...) /* synthesis multstyle = "dsp" */;
 Verilog-2001
(* multstyle = "dsp" *) module my_module(...);

When applied to a Verilog HDL variable declaration, the attribute specifies the implementation style for a multiplication operator, which has a result directly assigned to the variable. The attribute overrides the multstyle attribute with the enclosing module, if present.

In these examples, the multstyle attribute applied to variable result directs the Quartus® Prime software to implement a * b in logic rather than the dedicated hardware.

Table 45.   Applying a multstyle Attribute to a Variable Declaration
HDL Code
 Verilog-2001
wire [8:0] a, b;
(* multstyle = "logic" *) wire [17:0] result;              
assign result = a * b;  //Multiplication must be
                        //directly assigned to result
Verilog-1995
wire [8:0] a, b;
wire [17:0] result /* synthesis multstyle = "logic" */;
assign result = a * b;  //Multiplication must be                         
                        //directly assigned to result

When applied directly to a binary expression that contains the * operator, the attribute specifies the implementation style for that specific operator alone and overrides any multstyle attribute with the target variable or enclosing module.

In this example, the multstyle attribute indicates that you must implement a * b in the dedicated hardware.

Table 46.  Applying a multstyle Attribute to a Binary Expression
HDL Code
Verilog-2001
wire [8:0] a, b;
wire [17:0] result;
assign result = a * (* multstyle = "dsp" *) b;
Note: You cannot use Verilog-1995 attribute syntax to apply the multstyle attribute to a binary expression.

When applied to a VHDL entity or architecture, the attribute specifies the default implementation style for all instances of the * operator in the entity or architecture.

In this example, the multstyle attribute directs the Quartus® Prime software to use dedicated hardware, if possible, for all multiplications inside architecture rtl of entity my_entity.

Table 47.  Applying a multstyle Attribute to an Architecture
HDL Code
VHDL
architecture rtl of my_entity is
	attribute multstyle : string;
	attribute multstyle of rtl : architecture is "dsp";
begin

When applied to a VHDL signal or variable, the attribute specifies the implementation style for all instances of the * operator, which has a result directly assigned to the signal or variable. The attribute overrides the multstyle attribute with the enclosing entity or architecture, if present.

In this example, the multstyle attribute associated with signal result directs the Quartus® Prime software to implement a * b in logic rather than the dedicated hardware.

Table 48.  Applying a multstyle Attribute to a Signal or Variable
HDL Code
VHDL
signal a, b : unsigned(8 downto 0);
signal result : unsigned(17 downto 0);

attribute multstyle : string;
attribute multstyle of result : signal is "logic";
result <= a * b;