DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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9.6.2. Zero Latency Example

In this example, sufficient delays in the design ensure that DSP Builder requires no extra automatic pipelining to reach the fMAX target (although DSP Builder distributes this user-added delay through the datapath). Thus, the reported latency is zero. DSP Builder inserts no extra pipelining registers in the datapath to meet fMAX and thus inserts no balancing registers on the channel and valid paths. The delay of the valid signal across the subsystem is zero clock cycles, as the Lat: 0 latency value on the ChannelOut block shows.
Figure 74. Latency Example with a User-Specified Delay