DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.4.10. IIR: Full-rate Floating-point

This design example implements a full-rate floating-point IIR filter.
This design demonstrates a single-channel second-order Infinite Impulse Response (IIR) filter running at the clock rate. Usually with such designs, closing the feedback loop is impossible at high clock rates. This design recursively expands the mathematical expression from the feedback in terms of earlier samples, which gives a feed-forward scalar product and a longer feedback loop. You can make the feedback loop long enough to add any length of pipelining at the expense of more resources for the expansion.

The model file is demo_full_rate_iir_floating.mdl.

Figure 47. IIR Second-Order Biquad