DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.6.4. Folded FIR Filter

This design example implements a simple non-symmetric FIR filter using primitive blocks, with a data sample rate much less than the system clock rate. This design example uses ALU folding to minimize hardware resource utilization.

The model file is demo_alu_fir..mdl.