DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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4.5.1. Automatic Testbench

Each IP library block, and each synthesized Primitive library block writes out test vectors to a stimulus file (*.stm) during a Simulink simulation run. DSP Builder creates an RTL testbench for each separate entity in your design (that is, for each IP block and Primitive subsystem). These testbenches replay the test vectors through the generated RTL, and compare the output from the RTL to the output from the Simulink model. If a mismatch at any cycle exists, the simulation stops and DSP Builder indicates an error. Use these DSP Builder automatic testbenches, to verify the correct behavior of the synthesis engine.

The automatic testbench flow uses a stimulate-and-capture method and is therefore not restricted to a limited set of source blocks. The Simulink simulation stores data at the inputs and outputs of each entity during simulation. Tthen the testbench for each entity uses this data as a stimulus and compares the ModelSim output to the Simulink captured output. The result indicates whether the outputs match when the valid signal is high.