DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.8.8. Rectangular Nested Loop

In this design example all initialization, step, and limit values are constant. At the corners (at the end of loops) there may be cycles where the count value goes out of range, then the output valid signal from the loop is low.

The token-passing structure is typical for a nested-loop structure. The bs port of the innermost loop (ForLoopB) connects to the bd port of the same loop, so that the next loop iteration of this loop starts immediately after the previous iteration.

The bs port of the outer loop (ForLoopA) connects to the ls port of the inner loop; the ld port of the inner loop loops back to the bd port of the outer loop. Each iteration of the outer loop runs a full activation of the inner loop before continuing on to the next iteration.

The ls port of the outer loop connect to external logic and the ld port of the outer loop is unconnected, which is typical of applications where the control token is generated afresh for each activation of the outermost loop.

The model file is forloop_rectangle.mdl.