DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.4.4. Filter Chain with Forward Flow Control

This design example builds a filter chain with forward flow control.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_filters_flow_control.m script.

The FilterSystem subsystem includes FractionalRateFIR, InterpolatingFIR, InterpolatingCIC, Const and Scale blocks.

The model file is demo_filters_flow_control.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.