DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents Running System-In-the-Loop

This walkthrough uses a DSP Builder design that implements a primitive FIR filter with memory-mapped registers for storing coefficients
Figure 31. FIR Filter with Memory-Mapped Registers


  1. In the design’s Control block ensure you turn on Generate Hardware.
  2. Simulate the model to generate RTL.
  3. Select a device-level sub-system in your design and click DSP Builder > New SIL Wizard.
  4. On the Parameters tab, specify the parameters.
  5. Click the Run tab and specify the run parameters