DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7.3. Interfaces with a Processor Bus

DSP Builder designs can interface with a processor bus. You can drag and drop any register in your design without manually creating address decoding logic and memory-mapped switch fabric generation.