DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022
Public

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14.1.7. Register Out (RegOut)

The RegOut block provides a register field that you can write to your model and read from the processor interface.
Table 82.  Parameters for the RegOut Block
Parameter Description
Register Offset Specifies the address of the register. Must evaluate to an integer address.
Most Significant Bit Specifies the MSB of the memory-mapped register in a processor word (allows different registers to share same address). When multiple RegBit, RegOut, and RegField blocks specify the same address, they refer to the same Avalon-MM register. To avoid conflicts, ensure that the ranges that you specify do not overlap.
Least Significant Bit Specifies the LSB of the memory-mapped register in a processor word (allows different registers to share same address). When multiple RegBit, RegOut, and RegField blocks specify the same address, they refer to the same Avalon-MM register. To avoid conflicts, ensure that the ranges that you specify do not overlap.
Description Text describing the register. The description is propagated to the generated memory map.
Sample Time Specifies the Simulink sample time.
Table 83.  Port Interface for the RegOut Block
Signal Direction Type Description
d Input Any fixed-point type Write data.
w Input Boolean Write enable.