DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.6.13. Tapped Line Delay (TappedLineDelay)

The DSP Builder TappedDelayLine block takes a single scalar signal a and an enable signal e and produces an enabled tapped delay line of signals as a vector, q, and a corresponding valid signal, qv. The block is either a Latch_0L or Latch_1L (depending on the Zero or One Initial Delay parameter) followed by a series of Latch_1Ls. The block forms a vector from all the latch outputs. By default, the vector has the least delayed signal at the top (unless you turn on Reverse order parameter). This block uses latches from the Control library. DSP Builder does not support vector signal input for this block.

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