DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.4.35. Loop

The Loop block maintains a set of counters that implement the equivalent of a nested for loop in software. The counted values range from 0 to limit values provided with an input signal.

When the go signal is asserted on the g input, limit-values are read into the block with the c input. The dimension of the vector determines the number of counters (nested loops). When DSP Builder enables the block with the e input, it presents the counter values as a vector value at the q output each cycle. The valid output is set to 1 to indicate that a valid output is present.

There are vectors of flags indicating when first values (output f) and last values (output l) occur.

A particular element in these vector outputs is set to 1 when the corresponding loop counter is set at 0 or at count-1 respectively.

Use the Loop block to drive datapaths that operate on regular data either from an input port or data stored in a memory. The enable input, and corresponding valid output, facilitate forward flow control.

For a two dimensional loop the equivalent C++ code to describe the general loop is:

for (int i = 0; i < c[0]; i++)

for (int j = 0; j < c[1]; j++) {

q[0] = i;

q[1] = j;

f[0] = (i==0);

f[1] = (j==0);

l[0] = (i==(c[0]-1));

l[1] = (j==(c[1]-1));


Table 211.  Port Interface for the Loop Block
Signal Direction Type Description Vector Data Support Complex Data Support
g Input Boolean Go. Yes No
c Input Unsigned integer Counter limit values. Yes No
e Input Boolean Enable. Yes No
v Output Boolean Valid. Yes No
q Output Unsigned integer Counter output values. Yes No
f Output Boolean First value flags. Yes No
l Output Boolean Last value flags. Yes No