DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.4.20. Variable-Rate CIC Filter

CIC filters are extremely hardware efficient, as they require no multipliers. You see CIC filters commonly in applications that require large interpolation and decimation factors. Usually the interpolation and decimation factors are fixed, and you can use the CIC IP block. However, a subset of applications require you to change the interpolation and decimation factors at run time. This design example shows how to build a variable-rate CIC filter from primitives. It contains a variable-rate decimating CIC filter, which consists of a number of integrators and differentiators with a decimation block between them, where the rate change occurs.

You can control the rate change with a register field, which is part of the control interface. The register field controls the generation of a valid signal that feeds into the differentiators.

The design example also contains a gain compensation block that compensates for the rate change dependent gain of the CIC. It shifts the input up so that the MSB at the output is always at the same position, regardless of the rate change that you select.

The associated setup file contains parameters for the minimum and maximum decimation rate, and calculates the required internal data widths and the scaling number. To change the decimation factor for simulation, adjust variable CicDecRate to the desired current decimation rate.

The model file is demo_vcic.mdl.