DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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4.5. Verifying your DSP Builder Advanced Blockset Design in the ModelSim Simulator

Verify your design in Simulink or the ModelSim simulator with the automatic testbench flow. Also, compare Simulink results with the generated RTL, on all synthesizable IP and primitive subsystems. This final verification before you port the design to system-level integration ensures you should not need to iterate your design.
Note: Intel recommends the automatic testbench flow.