DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.8.3. Kronecker Tensor Product

This design example generates a Kronecker tensor product. The design example shows how to use the Loop block to generate datapaths that operate on regular data.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks.

The Chip subsystem includes the Device block and a lower-level KroneckerSubsystem subsystem.

The KroneckerSubsystem subsystem includes ChannelIn, ChannelOut, Loop, Const, DualMem, Mult, and SynthesisInfo blocks.

In this design example, the top level of the FPGA device (marked by the Device block) and the synthesizable KroneckerSubsystem subsystem (marked by the SynthesisInfo block) are at different hierarchy levels.

The model file is demo_kronecker.mdl.