DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.13.8. 4-Carrier, 4-Antenna DUC and DDC for LTE

These DUC and matching DDC designs connect to 4 antennas and can process 4 channels per antenna. With a sample rate of 61.44 MHz and a clock rate of 491.52 MHz, these designs represent up- and downconverters used in LTE.


The top-level design of the upconverter contains a TEST_BENCH block with signal sources, the upconverter, and a SINKS block that stores the datastreams coming out of the upconverter in MATLAB variables. Depending on which simulation you run, the TEST_BENCH block uses either real LTE sample streams or specialized debugging patterns. The upconverter consists of the LDUC module, the lower DUC, which contains a channel filter and two interpolating filters, each interpolating by a factor of 2. The filtered sample stream feeds into the COMPLEX MIXER block, where a NCO generates separate frequencies for each of the four channels, and multiplies the generated sinewaves with the filtered sample stream. A delay match block ensures that the sample stream and the generated frequencies align correctly. After the COMPLEX MIXER block is an antenna summer block, which adds up the different channels for each antenna, multiplies each with a different frequency, and outputs them to the four separate antennas.

The model file is duc_4c4ant.mdl.


The top-level design of the DDC also contains a TESTBENCH block, which contains source blocks that read from workspace. It uses the data that DSP Builder generates during the simulation of the DUC. The SINKS block again traces the outputs of the design in MATLAB variables, which you can analyze and manipulate in MATLAB. The DDC consists of a complex mixer that matches the complex mixer of the DUC, and the LDDC (Lower DownConverter), which contains two decimate-by-2 filters and a channel filter.

The model file is ddc_4c4ant.mdl.

Simulation Scripts

The design, which is in the Examples\ReferenceDesigns\DDC4c4ant\4C4T4R_echodemo\4C4T4R\Design directory, contains two separate parts: duc_4c4ant.mdl contains the upconverter, and ddc_4c4ant.mdl contains the downconverter. The directory also contains two scripts that allow you to run the simulation of both designs: Both Run_DUC_DDC_demo.m and Test_DUC_DDC_demo.m create test vectors, run the upconverter first, which generates the input vectors for the downconverter, - then run the downconverter and analyze the outputs. The designs contains no channel model, but you can add your own channel model and apply it to the output data of the DUC before running the DDC to simulate more realistic operating conditions. Run_DUC_DDC_demo.m uses typical LTE waveforms; Test_DUC_DDC_demo.m works with ramps that help visualizing which data goes into which channel and which antenna it transmits on. In the test pattern, an impulse is set first, followed by a ramp on channel 1 on antenna 1. All other channels and antenna are 0. The next section transmits channel 1 on antenna 1, channel 2 on antenna 2 … channel 4 on antenna 4. The last section transmits all 4 channels on all 4 antennas, using the full capacity of the system. Use this debug pattern, if you want to modify or extend the design. Run the scripts using the echodemo command, to step through the script section by section, by typing echodemo Run_DUC_DDC_demo.m at the MATLAB command prompt, and then clicking Next several times to step through the simulation script. Alternatively, you can run the entire script by typing Run_DUC_DDC_demo.m at the MATLAB command prompt. The last step of the script calls up a plot function that generates input vs output plots for each channel, with overlaid input and output plots. These plots should match closely, displaying only a small quantization error. The script also produces channel scopes, which show each channel’s data in time and frequency domains.