DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents Restrictions for DSP Builder Designs with Avalon Streaming Interface and AXI4-Stream Blocks

You can place the Avalon streaming interface and AXI4-Stream blocks in different levels of hierarchy. However, never place Simulink, IP or Primitive library blocks between the interface and the device level ports.

The Avalon streaming interface and AXI4-Stream specifications only allows a single data port per interface. Thus you may not add further data ports, or even using a vector through the interface and device-level port (which creates multiple data ports).

To handle multiple data ports through a single Avalon streaming interface or AXI4-Stream, pack them together into a single (not vector or bus) signal, then unpack on the other side of the interface. For the maximum width for a data signal, refer to the Avalon Interface Specifications.

Use the BitCombine and BitExtract blocks to pack and unpack.