DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.4.8. Half-Band FIR Filter

This design example implements a half band interpolating FIR filter.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_firih.m script.

The FilterSystem subsystem includes the Device block and two separate InterpolatingFIR blocks for the regular and interpolating filters.

The model file is demo_firih.mdl.

This design example uses the Simulink Signal Processing Blockset.