DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.12.10. Fractional Square Root Using CORDIC

This design example demonstrates CORDIC techniques, but does not use the CORDIC block. This design example is fully iterative.

The design example allows you to generate a valid signal. The design example only generates output and can only accept input every N cycles, where N depends on the number of stages, the data output format, and the target fMAX. The valid signal goes high when the output is ready. You can use this output signal to trigger the next input, for example, a FIFO buffer read for bursty data.

The model file is demo_cordic_fracsqrt.mdl.