DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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5.5. Simulating the RTL of the Fibonacci Design


To verify that DSP Builder gives the same results when you simulate the generated RTL, click on the Run ModelSim block.
Figure 36. Fibonacci Sequence in the ModelSim Wave Window
Compile the design in the Quartus Prime software.