DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents

6.2. Simulating the IP Design in Simulink

Create an IP design.


  1. In the demo_firi window, click Start > Simulation .
    MATLAB generates output HDL for the design.
  2. Click DSP Builder Resource Usage Design.
    You can view the resources of the whole design and the subsystems.
  3. Click Close.
  4. Double click the FilterSystem subsystsem, right-click on the filter1 InterpolatingFIR block, and click Help.

    After simulation, DSP Builder updates this help to include the following information:

    • The latency of the filter
    • The port interface
    • The input and output data format
    • The memory interface for the coefficients.
  5. To display the latency of the filter on the schematic, right-click on InterpolatingFIR block and click Block Properties.
  6. On the Block Annotation tab, in block property tokens double-click on %<latency>.
  7. In Enter text and tokens for annotation, type Latency = before %<latency>. Click OK.
    DSP Builder shows the latency beneath the block.
Verify the design in MATLAB. Compile the design in the Quartus Prime software