DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.12.18. Multichannel IIR Filter

This DSP Builder design example implements a masked multi-channel infinite impulse response (IIR) filter with a masked subsystem that it builds from Primitive library blocks.

This design example has many feedback loops. The design example implements all the pipelined delays in the circuit automatically. The multiple channels provide more latency around the circuit to ensure a high clock frequency result. Lumped delays allow you to easily parameterize the design example when changing the channel counts. For example, masking the subsystem provides the benefits of a black-box IP block but with visibility.

The top-level testbench includes Control and Signals blocks, plus ChanView block that deserialize the output buses.

The IIRChip subsystem includes the Device block and a masked IIRSubsystem subsystem. The coefficients for the filter are set from [b, a] = ellip(2, 1, 10, 0.3); in the callbacks for the masked subsystem. You can look under the mask to see the implementation details of the IIRSubsystem subsystem which includes ChannelIn, ChannelOut, SampleDelay, Const, Mult, Add, Sub, Convert, and SynthesisInfo blocks.

The model file is demo_iir.mdl.