DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents Sample Rate

The DSP Builder sample rate may exceed the FPGA clock rate, such as in a super sample rate system, for example in high-speed wireless front-end designs. In a radar or direct RF system with GHz digital-to-analog converters (DAC), the signal driving the DAC can have a sample rate in the GHz range. These high-speed systems require innovative architectural solutions and support for high-speed parallel processing. DSP Builder advanced blockset interpolation filter IP has built in support for super-sample rate signals, and the vector support of its Primitive library makes it easy for you to design your super-sample rate module. However, for a super-sample rate design, you must understand how channels are distributed across multiple wires as arrays, and how they are allocated among time slots available on each wire.

Use the following variables to determine the number of wires and the number of channels each wire carries by parameterization:

  • ClockRate is the system clock frequency.
  • SampleRate is the data sample rate per channel (MSPS).
  • ChanCount is the number of channels.
Note: Channels are enumerated from 0 to ChanCount – 1.
  • The Period (or folding factor) is the ratio of the clock rate to the sample rate and determines the number of available time slots:

    Period = max(1, floor(ClockRate/SampleRate))

  • The WiresPerChannel is the number of wires per channel:

    WiresPerChannel = ceil(SampleRate/ClockRate)

  • The WireGroups is the number of wire groups to carry all the channels regardless of channel rate:

    WireGroups = ceil(ChanCount / Period);

  • The number of channel wires the design requires to carry all the channels is the number of channels divided by the folding factor (except for supersampled filters):

    ChanWireCount = WiresPerChannel × WireGroups

  • The number of channels carried per wire is the number of channels divided by the number of channels per wire:

    ChanCycleCount = ceil(ChanCount/WireGroups)

Note: The channel signal counts through 0 to ChanCycleCount – 1.