DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents Periods

For any data signal in a DSP Builder design, the FPGA clock rate to sample rate ratio determines the period value of this data signal. In a multirate design, the signal sample rate can change as the data travels through a decimation or interpolation filter. Therefore period at different stages of your design may be different.

In a multichannel design, period also decides how many channels you can process on a wire, or on one signal. Where you have more channels than you can process on one path, or wire, in a conventional design, you need to duplicate the datapath and hardware to accommodate the channels that do not fit in a single wire. If the processing for each channel or path is not exactly the same, DSP Builder advanced blockset supports vector or array data and performs the hardware and datapath duplication for you. You can use a wire with a one dimensional data type to represent multiple parallel datapaths. DSP Builder IP and Primitive library blocks, such as adder, delay and multiplier blocks, all support vector inputs, or fat wires, so that you can easily connect models using a single bus as if it is a single wire.