DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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11.7.2. Improving DSP Builder Floating-Point Designs

In floating-point designs when comparing against zero, many of the samples never terminate and circulate through the feedback loop indefinitely. Because of the round-off errors accumulating in the NewtonStep subsystem, the residue may never reach exactly zero for many of the data samples.


  1. Use a subsystem to detect convergence and divergence of the iterative feedback loop
  2. Simulate the design. The number of valid samples on the output far exceeds the number of valid samples on the input.
  3. To track which pipeline slots contain a valid sample, add a control signal path that lies parallel to the datapath feedback.
  4. This 1-bit wide control path must be the same latency as the datapath.
    1. Ensure that for both SampleDelay blocks you turn on Minimum delay enabled.
    2. Set the Equivalence Group to the string, newton. When a sample converges to a root, DSP Builder outputs it as a valid solution and marks the pipeline slot as empty. If a sample diverges, DSP Builder marks the pipeline slot as empty but keeps valid low.
  5. Simulate this version of the design and verify that the number of valid samples output equals the number of valid samples input.
    The design may exceed the pipeline capacity if you provide too many valid samples on the input. The scheduled size of the sample delays indicates the maximum number of pipeline slots that are available for iterative computation. If you input more than this number, you risk overwriting previous valid samples before their iteration converges.
  6. To overcome this limitation, introduce a FIFO buffer for the input samples. When an empty pipeline slot becomes available at the front of the pipeline, DSP Builder removes a sample from the queue from the FIFO buffer and inserts it into the free slot to begin iterating around the NewtonStep feedback loop.
  7. Simulate the design and verify that you can safely input more valid samples than the pipeline depth of the iterative loop.
  8. Set the size of the FIFO buffer to adjust the capacity and ensure that it is as large as your application requires.
  9. The rounding errors of the floating-point blocks can interact in such a way that a sample forever oscillates between two values: never converging and never diverging. To detect this oscillation add another control path in parallel to the datapath feedback to count the number of iterations each sample passes through.
    Note: The TooMany subsystem compares the iteration count against a threshold to detect divergence.
    Note: The Mandelbrot_S design example implements another iterative algorithm that shows parallel feedback loops for floating-point data and control paths.
    Note: The matmul_CS design example exploits both vector and pipeline parallelism. This example also shows how to incorporate memories in the feedback path to store intermediate results.

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