DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents

7.4.15. Root-Raised Cosine FIR Filter

This design example uses the Decimating FIR block to build a 4-channel decimate by 5, 199-tap root raised cosine filter with a target system clock frequency of 304 MHz.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_fir_rrc.m script.

The FilterSystem subsystem includes the Device and Decimating FIR blocks.

The model file is demo_fir_rrc.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.