DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.12.21. Run-time Configurable Decimating and Interpolating Half-Rate FIR Filter

This design example contains a half-rate FIR filter, which can perform either decimation or interpolation by a factor of two during run time.

In decimation mode, the design example accepts a new sample every clock cycle, and produces a new result every two clock cycles. When interpolating, the design example accepts a new input every other clock cycle, and produces a new result every clock cycle. In both cases, the design example fully uses multipliers, making this structure very efficient compared to parallel instantiations of interpolate and decimate filters, or compared to a single rate filter with external interpolate and decimate stages.

The coefficients are set to [1 0 3 0 5 6 5 0 3 0 1] to illustrate the operation of the filter in setup_demo_fir_tdd.m.

The model file is demo_fir_tdd.mdl.