DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.4.16. Single-Rate FIR Filter

This design example uses the SingleRateFIR block to build a 16-channel single rate 49-tap FIR filter with a target system clock frequency of 360 MHz.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_firs.m script.

The FilterSystem subsystem includes the Device and SingleRateFIR blocks.

The model file is demo_firs.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.