DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents System-In-The-Loop Supported Blocks

System-in-the-loop only supports DSP Builder device-level blocks. The block interface may have complex and vector type ports.

All block input and output ports should pass through a single DSP Builder ChannelIn or ChannelOut interface, or be connected to a single IP block. The block may contain memory-mapped registers and memory blocks (accessible through the autogenerated Avalon memory-mapped agent interface). Observe the following limitations:

  • The design should use the same clock for system and bus interfaces. The design does not support separate clocks.
  • For autogenerated Avalon memory-mapped agent interfaces, use the name bus.
  • The design does not support any other combination of DSP Builder block interface, including Avalon memory-mapped hostr interfaces.

The overall bitwidth of block input and output ports should not exceed 512 bits (excluding the valid signal).

Running hardware verification with Data Sample Stepping loads a new set of test data to FPGA every simulation step (if the data set is valid), which gives big timing gaps between two subsequent cycles for DSP Builder blocks running on hardware. If your DSP Builder block implementation cannot handle such gaps, system-in-the-loop simulation results may be incorrect.