DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.13.21. Reconfigurable Decimation Filter

The reconfigurable decimation filter reference design uses primitive blocks to build a variable integer rate decimation FIR filter.

The reference design has the following features:

  • Supports arbitrary integer decimation rate (including the cases without rate change), arbitrary number of channels and arbitrary clock rate and input sample rate, if the clock rate is high enough to process all channels in a single data path (i.e. no hardware duplication).
  • Supports run-time reconfiguration of decimation rate.
  • Uses two memory banks for filter coefficients storage instead of prestoring coefficients for all rates in memory. Updates one memory bank while the design is reading coefficients from the other bank.
  • Implements real time control of scaling in the FIR datapath.

You can modify the parameters in the setup_vardownsampler.m file, which you access from the Edit Params icon.

The model file is vardownsampler.mdl.