DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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6.4. Reparameterizing the DSP Builder FIR Filter to Double the Number of Channels

Create an IP design.


  1. Double-click the EditParams block to open setup_my_firi.m in the MATLAB Editor. Change my_firi_param.ChanCount to 32 and click Save.
  2. Simulate the design.
    On the filter1 InterpolatingFIR block the latency and the number of multipliers increases
  3. On the DSP Builder menu, click Verify Design, and click Clear Results to clear the output pane. Turn on Verify at device level and Run Quartus Prime Software only, turn off Verify at subsystem level, and click Run Verification
    The Simulink simulation matches a ModelSim simulation of the generated HDL. The design meets timing but the number of multipliers and logic increases. The number of channels doubles, but the number of multipliers does not double, because the design shares some multipliers.
The design now closes timing above 480 MHz. At the higher clock rate, the design shares multiplier resources, and the multiplier count decreases back to 6.