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- 15.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 15.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
15.3.15. Multiwire Transpose (MultiwireTranspose)
Each element in the block has a logical address, which DSP Builder forms by concatenating its spatial address (wire number) with its temporal address (slot number). The spatial address is the least-significant part of the logical address; the temporal address is the most significant part.The block specifies the reordering as an arbitrary permutation of the address bits.The block numbers the address bits from 0 (least significant). The block specifies the permutation by listing the address bits in order, starting with the least significant.
For example: specifying:
[7 6 5 4 3 2 1 0] bit-reverses a block of 256 elements
[6 7 4 5 2 3 0 1] digit reverses a block (radix 4)
[0 1 2 3 4 5 6 7] leaves the order of the data unchanged
[6 7 0 1 2 3 4 5] rotates the address bits
[2 3 4 5 6 7 0 1] is be the inverse rotation.
|Address permutation||A vector of integers that describes how to rearrange the block of data.|
|N||The number of spatial address bits. The block has 2N data wires.|
|v||Input||Boolean.||Input valid signal.|
|d||Input||Any type.||Data input.|
|qv||Output||Boolean.||Output valid signal.|
|q||Output||Same as d||Data output.|
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