DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.12.12. Gaussian Random Number Generator

This DSP Builder design example demonstrates a random number generator (CLT component method) that produces random numbers with normal distribution and standard deviation that you specify using the input sigma_input.

You can also specify the seed value for the random sequence using the seed_value input. The reset input resets the sequence to the initial state defined by the seed_value. The output is a 32-bit single-precision floating-point number.