DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.12.25. Vector Sort—Sequential

This design example sorts the values on the input vector from largest to smallest. The sorting is a configurable masked subsystem: sortstages.

For sorting, the sortstages subsystem allows either a comparator and mux based block, or one based on a minimum and a maximum block. The first is more efficient. Both use the reconfigurable subsystem to choose between implementations using the BlockChoice parameter.

The design repeatedly uses a dual sort stage in series. The data passes through the dual sort stage (vector width)/2 times.

Look under the mask to view the implementation of reconfigurable subsystem templates and the blocks that reorder and interleave vectors.

The model file is demo_vectorsort.mdl.