DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.2.2. FFT without BitReverseCoreC Block

This design example implements a 2,048 point, radix 22 FFT. This design example accepts natural order or bit-reversed data at the input and produces bit-reversed or natural order data at the output, respectively. The design example is identical to the FFT design example, but it does not include a BitReverseCoreC block, which converts the input data stream from natural order to bit-reversed order.

Note: The FFT designs do not inherit width in bits and scaling information. The design example specifies these values with the Wordlength and FractionLength variables in the setup script, which are 16 and 19 for this design example. You can also set the maximum width in bits by setting the MaxOut variable. Most applications do not need the maximum width in bits. To save resources, set a threshold value for this variable. The default value of inf allows worst case bit growth.

The model file is demo_fft_core.mdl.