DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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11.6.4. DSP Builder Testbench Verification

The Simulink simulation model generates the stimulus files for the automated testbench. A multiple precision floating-point library processes the variable precision floating-point signal values. All functions round the output results to the nearest representable value, even if you configure the fundamental operators to use faithful rounding. Also, the elementary mathematical functions do not need to round to nearest to comply with the IEEE754 standard. Hence, the hardware does not always output the same bit pattern as the Simulink simulation. The benefit of this minor non-compliance with the IEEE standard is a potential improvement in quality of results, namely some combination of increased fMAX, reduced latency, and reduced area. DSP Builder provides tools to help analyze floating-point signals when simulating your designs.