DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents

4.6.2. Hardware Verification with System-in-the-Loop

Intel provides the system-in-the-loop flow for hardware verification.


  • Automatically generates HW verification system for DSP Builder designs based on your configuration.
  • Provides a wizard-based interface to configure, generate, and run HW verification system.
  • Provides two separate modes:
    • Run Test Vectors loads and runs test vectors with large chunks (based on test memory size on target verification platform)
    • Data Sample Stepping loads one set sample at a time while stepping through Simulink simulation

Data Sample Stepping generates a copy of the original model and replaces the DSP Builder block with a special block providing connection to the FPGA to process data.