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- 15.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)
- 15.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle)
7.13.3. 1-Antenna WiMAX DUC
The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. The design includes an Edit Params block to allow easy access to the setup variables in the setup_wimax_duc_1tx.m script.
The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC2Channel subsystem which contains SingleRateFIR, Scale, InterpolatingFIR, NCO, and ComplexMixer blocks. The deinterleaver subsystem contains a series of Primitive blocks including delays and multiplexers that deinterleave the two I and Q channels.
The FIR filters implement an interpolating filter chain that up converts the two channels from a frequency of 11.2 MSPS to a frequency of 89.6 MSPS (a total interpolating rate of 8). The complex mixer and NCO modulate the two input channel baseband signals to the IF domain. The design configures the NCO with a single channel to provide one sine and one cosine wave at a frequency of 22.4 MHz. The NCO has the same sample rate (89.6 MSPS) as the input data sample rate.
A system clock rate of 179.2 MHz drives the design on the FPGA, which the Device block defines inside the DUCChip subsystem.
The model file is wimax_duc_1tx.mdl.
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