DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents

7.8.5. Primitive FIR with Back Pressure

This DSP Builder design example uses Primitive library blocks to implement a FIR design with flow control and back pressure. The design example shows how you use the Primitive FIFO block to implement back pressure and flow control.

The top-level testbench includes Control and Signals blocks.

The FirChip subsystem includes the Device block and a lower-level primitive FIR subsystem.

The primitive FIR subsystem includes ChannelIn, ChannelOut, FIFO, Not, And, Mux, SampleDelay, Const, Mult, Add, and SynthesisInfo blocks.

In this design example, the top level of the FPGA device (marked by the Device block) and the synthesizable Primitive FIR subsystem (marked by the SynthesisInfo block) are at different hierarchy levels.

The model file is demo_back_pressure.mdl.

This design example shows how back pressure from a downstream block can halt upstream processing. This design example provides three FIR filters. A FIFO buffer follows each FIR filter that can buffer any data that is flowing through the FIFO buffer. If the FIFO buffer becomes half full, the design asserts the ready signal back to the upstream block. This signal prevents any new input (as flagged by valid) entering the FIR block. The FIFO buffers always show the next data if it is available and the valid signal is asserted high. You must AND this FIFO valid signal with the ready signal to consume the data at the head of the FIFO buffer. If the AND result is high, you can consume data because it is available and you are ready for it.

You can chain several blocks together in this way, and no ready signal has to feed back further than one block, which allows you to use modular design techniques with local control.

The delay in the feedback loop represents the lumped delay that spreads throughout the FIR filter block. The delay must be at least as big as the delay through the FIR filter. This delay is not critical. Experiment with some values to find the right one. The FIFO buffer must be able to hold at least this much data after it asserts full. The full threshold must be at least this delay amount below the size of the FIFO buffer (64 – 32 in this design example).

The final block uses an external ready signal that comes from a downstream block in the system.