DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.4.19. Super-Sample Interpolating FIR Filter

This design example shows how the filters cope with data rates greater than the clock rate. The design example uses the InterpolatingFIR block to build a single channel interpolate by 3, symmetrical, 33-tap FIR filter.

The input sample rate is twice the clock rate and is interpolated by three by the filter to six times the clock rate, which is visible in the vector input and output data connections. The input receives two samples in parallel at the input, and six samples are output each cycle.

After simulation, you can view the resource usage.

The model file is demo_ssfiri.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.