DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.4.6. Fractional FIR Filter Chain

This design example uses a chain of InterpolatingFIR and DecimatingFIR blocks to build a 16-channel fractional rate filter with a target system clock frequency of 360 MHz.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_fir_fractional.m script.

The FilterSystem subsystem includes ChanView, Decimating FIR, InterpolatingFIR, and Scale blocks.

The model file is demo_fir_fractional.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.