DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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14.2.3. Avalon-ST Output (AStOutput)

Place this block at the back end of a system to generate the appropriate hw.tcl code for an Avalon Streaming interface with same name as the name of this block.
Table 88.  AStOutput Block External Interface Signals
Name Direction Description
source_channel Output Channel number.
source_data Output The data to be output (which may be, or include control data).
source_eop Output Indicates end of packet,
source_ready Input Indicates from downstream components that they can accept source_data on this rising clock edge.
source_sop Output Indicates start of packet.
source_valid Output Indicates that source_data, source_channel, source_sop, and source_eop are valid.
Table 89.  AStOutput Block Internal Interface Signals
Name Direction Description
output_channel input Channel number.
output_data input The output data (which may be, or include control data).
output_eop input Indicates end of packet.
output_ready output Indicates from the output of the DSP Builder component that it can accept sink_data on this rising clock edge.
output_sop input Indicates start of packet.
output_valid input Indicates that output_data, output_channel, output_sop, and output_eop are valid.

The downstream system component may not accept data and so may back pressure this block by forcing Avalon ST signal source_ready = 0. However, thedesign may still have valid outputs in the pipeline. You must store these outputs in memory. DSP Builder writes the output data for the design into a data FIFO buffer, with the Avalon-ST signals channel. It writes sop and eop into the respective channel, FIFO buffers.

Connect the backpressure signal (source_ready) from downstream components to port ready in this subsystem. Then DSP Builder reads the FIFO buffers when the downstream block can accept data (read_fifo = 1) and data in FIFO to output (fifo_empty_n = 1) exists.

If the downstream component is continually backpressuring this design, these FIFO buffers start to fill up. If you continue to feed data into the component, eventually the FIFO buffers overflow, which you must not allow to happen. Therefore, when the FIFO buffers reach a certain fill level, they assert signal nearly_full = 1. Use this signal to apply backpressure to upstream component (forcing Avalon ST signal sink_ready = 0). So that upstream components stop sending in more data and so that the FIFO buffer should not overflow, set the fill level at which nearly_full = 1 to a value that depends on the latency of this design. For example, if the design contains a single Primitive subsystem and the ChannelOut block indicates a latency of L, assert the nearly_full flag at the latest point when L free entries are in the FIFO buffer. Setting this threshold is a manual process and the full threshold must be greater than or equal to 
(depth of FIFO buffer – L).