DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.13.2. 2-Antenna WiMAX DDC

This reference design uses IP and Interface blocks to build a 4-channel, 2-antenna, 2-frequency modulation DDC for use in an IF modem design compatible with the WiMAX standard.

The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. the design includes an Edit Params block to allow easy access to the setup variables in the setup_wimax_ddc_2rx_iiqq.m script.

The DDCChip subsystem includes Device, Decimating FIR, Mixer, NCO, SingleRateFIR, and Scale blocks.

The FIR filters implement a decimating filter chain that down convert the two channels from a frequency of 89.6 MSPS to a frequency of 11.2 MSPS (a total decimation rate of 8). The real mixer and NCO isolate the two channels. The design configures the NCO with two channels to provide two sets of sine and cosine waves at the same frequency of 22.4 MHz. The NCO has the same sample rate of (89.6 MSPS) as the input data sample rate.

A system clock rate of 179.2 MHz drives the design on the FPGA, which the Device block defines inside the DDCChip subsystem.

The model file is wimax_ddc_2rx_iiqq.mdl.

Note: This reference design uses the Simulink Signal Processing Blockset.