DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.4.21. Counter

The Counter block maintains a counter and outputs the counter value each cycle.

The input is a counter enable and allows you to implement irregular counters. The counter initializes to the value that you provide, and counts with the modulo, with the step size you provide:

count = _pre_initialization_value;

while (1) { if (en) count = (count + _step_size) % _modulo}

Note: If you create a counter with a preinitialization value of 0 and with a step of 1, it outputs the value 1 (not 0) on its first enabled cycle. If you want the counter to output 0 on its first valid output, initialize with:

[<(modulo – step size)> <modulo> <step size>]

Note: Modulo and step size cannot be coprime—the step size must exactly divide into the modulo value.
Table 185.  Parameters for the Counter Block
Parameter Description
Output data type mode Determines how the block sets its output data type:
  • Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types.
  • Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. This option reinterprets the output bit pattern from the LSB up according to the specified type.
  • Boolean: the output type is Boolean.
Output data type Specifies the output data type. For example, sfix(16), uint(8).
Output scaling value Specifies the output scaling value. For example, 2^-15.
Counter setup A vector that specifies the counter in the format:

[<pre_initialization_value> <modulo> <step size>]

For example, [0 32 1]

Table 186.  Port Interface for the Counter Block
Signal Direction Type Description Vector Data Support Complex Data Support
en Input Boolean Count enable Yes No
q Output Specified fixed-point type Result Yes No