DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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7.13.22. Single-Channel 10-MHz LTE Transmitter

This reference design uses IP, Primitive, and blocks from the FFT Blockset library to build a single-channel 10-MHz LTE transmitter.

The top-level testbench includes blocks to access control and signals, and to run the Quartus Prime software. It also includes an Edit Params block to allow easy access to the configuration variables in the setup_sc_LTEtxr.m script. A discrete-time scatter plot scope displays the constellation of the modulated signal in inphase versus quadrature components.

The LTE_txr subsystem includes a Device block to specify the target FPGA device, and 64QAM, 1K_IFFT, ScaleRnd, CP_bReverse, Chg_Data_Format, and DUC blocks.

The 64QAM subsystem uses a lookup table to convert the source input data into 64 QAM symbol mapped data. The 1K_IFFT subsystem converts the frequency domain quadrature amplitude modulation (QAM) modulated symbols to the time domain. The ScaleRnd subsystem follows the conversion, which scales down the output signals and converts them to the specified fixed-point type.

The bit CP_bReverse subsystem adds extended cycle prefix (CP) or guard interval for each orthogonal frequency-domain multiplexing (OFDM) symbol to avoid intersymbol interference (ISI) that causes multipaths. The CP_bReverse block reorders the output bits of IFFT subsystems, which are in bit-reversed order, so that they are in the correct order in the time domain. The design adds the cyclic prefix bit by copying the last 25% of the data frame, then appends to the beginning of it.

The Chg_Data_Format subsystem changes the output data format of CP_bReverse subsystem to match the working protocol format of DUC subsystem.

The DUC subsystem uses an interpolating filter chain to achieve an interpolation factor of 16, such that the design interpolates the 15.36 Msps input channel to 245.76 Msps. In this design, an interpolating finite impulse response (FIR) filter interpolates by 2, followed by a cascaded integrator-comb (CIC) filter with an interpolation rate of 8. An NCO generates orthogonal sinusoids at specified carrier frequency. The design mixes the signals with complex input data with a ComplexMixer block. The final SINC compensation filter compensates for the digital analog converter (DAC) frequency response roll-off.

A system clock rate of 245.76 MHz drives the design on the FPGA. The Signals block of the design defines this clock. The input random data for the 64QAM symbol mapping subsystem has a data rate of 15.36 Msps.

The model file is sc_LTEtxr.mdl.