DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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Document Table of Contents Multichannel Systems with IP Library Blocks

IP library blocks are vectorizable, if data going into a block is a vector requiring multiple instances. For example, for a FIR filter, DSP Builder creates multiple FIR blocks in parallel behind a single IP block. If a decimating filter requires a smaller vector on the output, DSP Builder multiplexes data from individual subfilters onto the output vector automatically, to avoid custom glue logic.

IP library blocks typically take a channel count as a parameter, which is simple to conceptualize. DSP Builder numbers the channels 0 to (N – 1), and you can use the channel indicator at any point to filter out some channels. To merge two streams, DSP Builder creates some logic to multiplex the data. Sequence and counter blocks regenerate valid and channel signals.