DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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15.4.7. AND Gate (And)

The And block outputs the logical AND of the input values.

If the number of inputs is set to 1, then the logical and of all the individual bits of the input word is output.


Table 161.  Parameters for the And Block
Parameter Description
Number of inputs Specifies the number of inputs.
Output data type mode Determines how the block sets its output data type:
  • Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types.
  • Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected. This option reinterprets the output bit pattern from the LSB up according to the specified type.
  • Boolean: the output type is Boolean.
Output data type Specifies the output data type. For example, sfix(16), uint(8).
Output scaling value Specifies the output scaling value. For example, 2^-15.


Table 162.  Port Interface for the And Block
Signal Direction Type Description Vector Data Support Complex Data Support
unnamed Input Any fixed-point type Operands 1 to n Yes No
q Output Derived fixed-point type Result Yes No