DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.27. Transmit and Receive Modem

The transmit and receive modem design contains a QAM transmitter, a synthesizeable channel model and a receiver, working at sample rates that match or exceed the clock rate. The design works at different sample rates, and can provide up to 16 parallel data streams between transmitter and receiver.

The transmitter can produce random data, which is useful for generating a hardware demo, or you can feed it with data from the MATLAB environment. You can modulate the data, where the modulation order can be QAM4 or QAM64. The design filters the signal, and then feeds it into optional crest factor reduction (CFR) and digital predistortion (DPD) blocks. Intel assumes you have a control processor that configures modulation scheme and CFR and DPD parameters.

The channel model contains a random noise source, and a channel model, which you can configure through the setup script. This channel model allows you to build a hardware demonstrator on a standard FPGA development platform, without DA or AD converters and analogue components. Following the channel model is the model of a decimating ADC, which emulates the behavior of some existing ADC components that provide this functionality.

The receiver contains an RRC filter, followed by an equalizer. Intel assumes that a control processor calculates the equalizer coefficients. The equalizer feeds into an AGC block, which feeds into a demapper. You can configure the demapper to different modulation orders.

The model file is tx_ch_rx.mdl