DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022

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9.8. Reset Minimization

Reset minimization reduces the amount of reset logic in your design A reduction in reset logic can give an area decrease and potential fMAX increase. Reset minimization removes resets on the datapath. You can apply reset minimization globally to floating-point operators and to your synthesizable subsystems. By default, DSP Builder turns on reset minimization for HyperFlex™ architectures and off for all other devices.

DSP Builder distinguishes control flow from data flow: control flow is the logic you connect to the ChannelIn and ChannelOut valid signal path. DSP Builder applies little or no reset minimization to control logic and aggressive minimzation to data flow.

By default, DSP Builder chooses reset minimization options for you automatically. It automatically applies reset minimization if your target device includes the HyperFlex architecture.

You may override the default automatic reset minimization options, for example as part of design space optimization.

When you globally apply reset minimization, DSP Builder determines a local reset minimization setting for each of your synthesizable subsystems. DSP Builder applies this local reset minimization conditionally, if your subsystem contains ChannelIn or ChannelOut blocks.

Table 25.  Reset Minimization SummaryIf your synthesizable subsystem uses a mixture of Channel and GP blocks, choose Conditional for Local reset minimization.
Global Enable Local Setting Synthesizable Subsystem Reset Minimization
Off Any Any No
On Off Any No
On Conditional ChannelIn and ChannelOut Yes
On Conditional GPIn and GPOut No
On On ChannelIn and ChannelOut Yes
On On GPIn and GPOut Yes

DSP Builder does not apply reset minimization to blocks with innate state, user-constructed cycles, and enable logic in your design, as that can give undefined initial values.

Reset minimization only detects local cycles within a subsystem. You should avoid broader feedback cycles.

Reset minimization may affect the behavior of your design during Simulink simulation and on hardware.

Simulink Simulation

The DSP Builder simulation engine within Simulink is unaware of the reset minimization optimization and therefore always simulates your design behavior with reset present.

In general there is no difference in behavior, and this is aided by the testbench inputs defaulting typically to zero and a longer minimum reset pulse-width allowing such defaults to propagate through the datapath register stages.

However in some cases mismatches may occur, because data entering a Sample Delay in your design during reset is non-zero.

If an input does not default to zero or the internal behavior is incompatible with Sample Delay blocks resetting to zeros (or the minimum reset-pulse width is less than the design latency), the Simulink simulation might be different than the HDL simulation.

Implementation on Hardware

Removing a reset on the datapath means that when DSP Builder releases a reset, your data flow logic may contain values clocked in during reset, which might affect the initial post-reset behavior of your system.

Reset minimization detects and avoids optimizing cycles in your synthesizable subsystem. It does not detect cycles constructed outside of a single synthesizable subsystem. Do not enable it for such designs.